I wish to use several AD75019 in a daisy chain to create a large switch matrix (between 6 and 16 of these chips), and I have been successful in controlling one of them so far.
When the chip is clocked, the data will eventually exit from SOUT on the positive edge of the clock.
However, the data is also clocked into the chip on the positive edge.
So when the SOUT data (which changes on the positive clock edge) is connected to the SIN of the next chip, how can it be expected to clock in the data reliably if both the output transitions and the input sampling are both happening on the positive edge of the clock ?
Does anyone have any more information about how this works. It seems that people have been successful doing this..however I don't see how it can work ? and have had some trouble getting it to work reliably.
Thanks for any suggestions.