I've been looking at the EVAL-AD7689EDZ recently, as I am trying to extract best performance from this device.
The SPI clock, under control of the AD software (and EVAL-CED1Z), changes frequency in steps, according to the sampling rate set by the user.
For example, I saw this:
sampling rate = 42 to 53 kHz, SPI clock = 12.5 MHz
sampling rate = 54 to 75 kHz, SPI clock = 16.6 MHz
sampling rate = 76 to 129 kHz, SPI clock = 25 MHz
sampling rate = 130 to 250 kHz, SPI clock = 50 MHz
So I'm wondering, is there any special reason for doing this, rather just than using the highest frequncy for all sampling rates? Does it have noise advantages?