Last time I asked the DPLL not lock under using AD9548 evaluation kit on board 50Mhz Xtal.
This time, I changed the clock input from the OXCO 10MHz.
The clock amplitude is 1.5Vpp at SYSCLKN pin.
The REFA input is 1pps signal from GPS module. Input amplitude 3.3Vpp, pulse width 100uS.
But the DPPL status still shows : Mode free run, no phase lock, no frequency lock.
I uploaded the output phase noise ( output frequency set to 10MHz) for reference, blue one is under 50MHz Xtal clock, red one is under 10MHz OXCO.
I also set the phase lock and frequency lock threshold to Max. And the R0x0600<7>=1, set to nano sec scale.
I also try to set the DDS from 62.5MHz to 160MHz, still not lock.
Any suggestion that I can measure the signal to check phase lock or frequency lock?
Or any setting I may miss or mistake?