We are using the External Port for accessing both SDRAM (SDC) and NAND Flash (AMI).
After accessing SDRAM (e.g. a read) by either core or DMA access it seems that the AMIMS bit in AMISTAT is 0 for a certain number of cycles. Means the SDRAM Controller controls the external bus. If we access the NAND shortly after a SDRAM access it (sometimes) conflicts.
I would like to know if we really need to wait for the AMIMS bit to go 1 before accessing the NAND via the AMI Interface. Does the SHARC not handle the bus switch itself (e.g. by blocking untill SDRAM bus access is completed)?