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AD8657ARMZ latch-up phenomena

Question asked by electricswitch on Apr 16, 2015
Latest reply on Aug 24, 2015 by mark.reisiger

Hello, Colleagues !

Looks like i have some problem with ADI's AD8657 op-amps under certain operating conditions. I attach my schematics so it might be easier to describe and understand the case:

zeta differential hi EMIRR v2 for problem report.jpg

A brief schematics description:

I have a prototype of a so-called paraphase precision amplifier based on the single AD8657 MSOP case with artificially generated common-point voltage sourcing from a buffer stage, based on the second AD8657 MSOP case. I also plan to design a SENSOR-DSP integrated module with linearized absolute output signal approx. 0 ... 2.5 V (DACOUT relative to AVSS).

So my differential amplifier stage acts like a common-mode to differential out converter, producing weak differential output signal of hundreds of millivolts (say, 0 ... 100 mV full-scale, fo fix an idea). You may also notice a MAXIM's precision 1:25 voltage divider on its input for that purpose.

You may also notice a VDDA line connected through 180k R22 to pin 5 of D3. This yields a small negative offset in output signal thus allowing my SENSOR-DSP module to rise its "payload" output slightly above absolute zero thus greatly improving output linearity around zero mV.

Another peculiarity as one could notice is that my SENSOR-DSP block is supposed to have a "floating" power-supply with its positive rail being tied to VLINE+ and its negative rail generated directly from a buffer based on D4. This is due to some power supply limitations of my future SENSOR-DSP module actually but i think it doesn't matter in our case.

A brief problem description:

First of all - everything goes well when i use an Agilent E3641A power supply for powering up my fixture (the whole part is supposed to be powered from 10 V DC). My output stage successfully drives a cable line of 2-5 meters long with measuring equipment on the other side and i cannot see any error.

The problem arises when i try to power my amplifier "by hand", i.e. holding positive rail wires with my fingers while connecting'em together. I can observe now an linear error up to +/- 5 mV in output signal with voltage at DACOUT  relative to AVSS being exactly the same !

A very interesting things were figured out when i tried to fall into this problem more deeply: when i try to measure a difference between pins 2-3 or pins 5-6 of D3, I always see around 3-10 uV in a normal state (a state with NO error at the output), and almost 3.7 mV (3.700 uV !) in an "error" state.

Trying to further investigate this case i also figured out that my error strongly depends on two facts:

1. Power supply slope at pins 8 and 4 of my op-amps when powering on.

2. A small leakage through the positive power line (for example through my fingers or moisture in the feeding electrical connector) into my experimental fixture (around 5 ... 20 uA).

An error appears only when two of the above conditions take place simultaneously. So if we exclude one of'em we get clear and stable output with absolutely no error.

Then, trying to find out what's going on, i've played with a power supply filter elements and figured out that the problem ceases completely if power supply edge at pins 8 (relative to pin 4) of op-amp is not shorter than approximately 600 uS and any leakage, i was talking about above, cannot cause error appearance in that case.

I also provide some oscilloscope shots made by me.

Yellow curves are voltage at pin 8 relative to pin 4 of op-amp.
Cyan curves are voltage level at power up at pin 5 relative to pin 4.
Magenta curves are voltage level at power up at pin 3 relative to pin 4.


Shot 1. A startup process seen with filter elements shown on schematic diagram above.

Failures were observed almost every power-on cycle.

Shot 2. A startup process seen with the sum of C1 and C2 equal to 4.7 uF (yeah, there were actually one cap instead of two).

Failures occur now approximately in 50% of power on cycles.


Shot 3. A startup process seen with 4.7 uF cap and both R1 and R2 increased up to 51 Ohms (more than twice relative to original schematics).

Failures now cannot be observed at all.


It is clearly seen that failure rate correlates clearly with power-up edge speed and depends also on where peaks of transients reside in time relative to power supply level. A slight offset before power up event caused by a small leakage described above is also can be noticed.

Some statistics:

I've tried more than two dozens of AD8657 chips i had (they all did not have the same lot no, some of them were manufactured on 2012, some of them are newer, some are very new - I use them widely in some of my lab tests due to their excellent EMI immunity). So only three of them exhibit such an effect persistently. Well .. actually others also do but i had to put some effort - (make more strong leakage, make much more power ons/offs and so on).

Some thoughts:

I use an excellent soldering equipment (JBC tools) and good anti-static working place so i don't think that a static discharge is likely to be the reason of damaging chips.

I also checked whole signal path for parasitic oscillations and noticed nothing bad (this is a quite stable op-amp and quite stable schematics, but **** .. who knows ..)

I haven't found any hints to my problem in the latest AD8657 datasheets, but i knew from literature that there may be a problem with MOS-structures latch-up due to very fast power supply edges but i always considered it a property of much more older and bigger chips (80's - 90's of the 20th century).

Some questions:

1. How do you think, what's that ? Is that really kind of a latch-up due to behaviour of some intrinsic parasitic structures present in the substrate of any MOS chip ?

2. Does anybody of your team know about such an effect ? I guess it would be very useful for developers if they could see some notes about it in the datasheet.

3. What's the most efficient way to eliminate such an effect for me ?


I'll be very appreciative for any help/advice !
Thank you in advance !