I am trying to evaluate SDR Partial Reconfiguration solution with ZC706 and fmcomm3 boards.
I had followed the all steps given in webpage
and generated all partial BIN file.
I am using hdl-hdl_2014_r2.zip FPGA reference design.
But Demo is not working.
When I am trying to change partial bitstream , the system getting hang. (screen become white).
Please suggest some solution to make this Demo.