as we know, ADV7125 data input timing specificaiton request as below:
the data obviously latched by the rising of the CLOCK
one of customer's timing specification as below
the time delay from CLOCK half voltage point to the Vih threshold is only 1.02ns.
the time delay from CLOCK half voltage point to the DATA rising edge only 0.5ns.
I don't think this timing is safe for any jitter on the CLOCK or DATA will cause wrong result.
could you help to confirm it?
AND, about the t1 and t2 measrement of the datasheet figure2, from datasheet, it's more like the time delay between CLOCK half-voltage point to the DATA half-voltage point, could you help to confirm it?