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LVDS Clock Jitter?

Question asked by CMC-B on Apr 13, 2015
Latest reply on Apr 17, 2015 by tlili

We have probed the differential LVDS Clock and seem to see a fair amount of jitter based on the eye diagram we observed (sorry I do not have a quantitative number to report to you).  We believe that this variation in the clock is leading to integrity issues in our HDL design that interfaces to two AD9361's.  Do you have any suggestions or comments on this topic?  I see from the data sheet that the CLK Pulse Width specification (tMP) is 45% - 55% of the CLK period, but I'm not sure that this would relate directly to the CL:K's jitter.


Thank You