I am working with AD9361 FMC card from quite a while. Till now successfully configured the chip to work perfectly in SDR mode, dual port in full duplex @ 30.72 MHz.
But while trying to configure it in DDR mode, dual port full duplex, I am not able to receive clean data_clk from the chip & hence no data is being transferred properly. Presently, using the AD936x evaluation software to generate the configuration script & load values in verilog code. All the status registers read through control_out pins are giving expected results. The chip is working in CMOS mode.
Not able to figure out the cause for this problem, so please can anyone suggest me where to look in for correction.