We are currently testing the AD9625. The SFDR is ~77 dBc. Do you know of a linearization algorithm that can be implemented in a FPGA to improve the SFDR?
Can you elaborate a bit on your request and what you mean by 'linearization algorithm'?
Please be sure that you are setting the trim value in register 0x121 for the actual sample rate that you are testing.
We are interested in adding digital post‑linearization to increase the effective resolution of ADC. The goal is to suppress low order non‑linearities of the ADC. I've seen a few papers online discussing this, and there is a company named SP Devices that sells IP for this. I would like to implement an algorithm in the FPGA that follows the ADC.
The AD9625 appears to meeting the SFDR as specified in the data sheet, ~77 dBc. We really need 10 dB better.
I will follow up with you further via email.
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