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AD8237 DC offset with Vref pin voltage drift

Question asked by m3atwad on Apr 10, 2015
Latest reply on Apr 16, 2015 by m3atwad



I'm using the AD8237 instrumentation amp in a design.  I'm trying to take two differential inputs in and convert them to a single ended output as well as add a dc offset.  I want the amp to output a dc bias/offset of 1.65V when there is no difference between Vin +/-.  This is because my Vcc is 3.3V and 3.3/2 = 1.65.  Therefore when my differential inputs diverge with Vin+ being a higher voltage than Vin- or when Vin- is a higher voltage than Vin+ I can see both because the output will fluctuate around 1.65V instead of 0V. 


Anyways, I've got this up and running on the bench pretty well with a voltage divider (tried 2x 10k's and 2x 1k's) which give me 3.3V/2 and I connect this to the Vref pin of the 8237.  This works until I start changing the differential inputs.  I set Vin- to 1.5V and increase V+ above 1.5V.  This changes my Vref voltage from my divider as I increase the V+ input.  As I increase V+ in this manner the voltage at my voltage divider increases to 1.7V.  If I set V+ to 1.5V and increase V- my Vref voltage changes to 1.6.  It's like it loses and gains 50mV when I change my inputs across my acceptable voltage range.  I've also tried buffering this with an op-amp so that the 1.65V from the voltage divider goes into the + input of an op amp set as a unity gain buffer.  When I connect the output to the Vref pin the Vref pin stays stuck at 1.7V +/- ~1mV.


I need help figuring out why my voltage at the Vref pin changes.  The problem I'm having is that when the Vref pin voltage changes it changes my output and therefore screws up my gain.  If it doesn't stay set right at 1.65 as I increase and decrease my differential inputs I can't calculate what my actual input differential is because Vref keeps changing.


For a schematic/diagram I'm using the same circuit shown in figure 72 of the data sheet.  I've also put a resistor in parallel with the Vref input and the divider as shown in figure 71.  This hasn't helped at all either.  I've set the gain of this test circuit to 6.


Any help is greatly appreciated.  I think this design will work if I can figure this out!