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ADV7611-Constant Output, despite changing color in Free-run mode

Question asked by puneet.a on Apr 9, 2015
Latest reply on Apr 24, 2015 by mattp

Hi,

I am facing some issue with ADV7611 with its RGB data Output.

 

We have programmed the device to output RGB24 bit data and we are running it in free-run mode without connecting anything at HDMI input.

We are getting the Pixel clock out with Hsync and Vsync signals also and pixel data is also coming out but the data is fixed no matter if we change the default blue color (in free run) to some other color by changing values in output color channel registers.

 

We will appreciate a fast response.

 

Following are the register settings that we are using:

Map Addresses

 

  (0x98, 0xFF, 0x80); IO REG map

  (0x98, 0xF4, 0x80); CEC map

  (0x98, 0xF5, 0x7c); Infoframe map

  (0x98, 0xF8, 0x4c); DPLL map

  (0x98, 0xF9, 0x64); Repeater map

  (0x98, 0xFA, 0x6c); EDID map

  (0x98, 0xFB, 0x68); HDMI map

  (0x98, 0xFD, 0x44); CP map

 

 

Register Settings

(0x98, 0x00, 0x08); // VGA, 640X460

(0x98, 0x01, 0x06); //HDMI Graphics

(0x98, 0x02, 0xf5); //- Input color space depends on color space reported by HDMI block; OP_656_RANGE; - Reverses OP_656_RANGE

(0x98, 0x03, 0x40); //24-bit 4:4:4 SDR mode

(0x98, 0x04, 0x62); // Xtal freq - - 24.567 MHz; o/p port- P[23:16] V/R, P[15:8] Y/G, P[7:0] U/CrCb/B (RGB)

(0x98, 0x05, 0x28); //No AV signal in data

(0x98,0x06,0xAE); //-ve pol on DataEnable

(0x98,0x0B,0x44); //Power up part

(0x98,0x0C,0x42); //Power up part

(0x98,0x14,0x7f); //drive strength max

(0x98,0x15,0x80); //Disable Tristate of Pins

(0x98,0x19,0xC3); //LLC DLL phase

(0x98,0x33,0x40); //LLC DLL enable

(0x44,0xBA,0x01); //Set HDMI FreeRun

(0x44,0xBF,0x13); //force CP in free run and o/p color blue

//  (0x44,0xBF,0x17); //force CP in free run and o/p color from cha, chb,chc

(0x44, 0xc9, 0x2d); //don't swap the LUMA and CHROMA in DDR mode, disable the buffer in HDMI mode

(0x64,0x40,0x81); //Disable HDCP 1.1 features

(0x68,0x9B,0x03); //ADI recommended setting

(0x68,0x00,0x08); //Set HDMI Input Port A (BG_MEAS_PORT_SEL = 001b)

(0x68,0x02,0x03); //Enable Ports A & B in background mode

(0x68,0x83,0xFC); //Enable clock terminators for port A & B

(0x68,0x6F,0x08); //ADI recommended setting

(0x68,0x85,0x1F); //ADI recommended setting

(0x68,0x87,0x70); //ADI recommended setting

(0x68,0x8D,0x04); //LFG Port A

(0x68,0x8E,0x1E); //HFG Port A

(0x68,0x1A,0x8A); //unmute audio

(0x68,0x57,0xDA); //ADI recommended setting

(0x68,0x58,0x01); //ADI recommended setting

(0x68,0x75,0x10); //DDC drive strength

(0x68,0x90,0x04); //LFG Port B

(0x68,0x91,0x1E); //HFG Port B

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