I am trying to understand how the JESD204 lane crossbar swapping is done for the AD9144 DAC in both the HDL and Linux driver/devicetree for the DAQ2 FMC and the being setup FMCOMMS7 design's.
I have studied the schematics, TCL build scripts, XDC pin out, and Linux DTS file for the DAQ2 and still do not quite understand just how the GT lane swapping ordering is setup. I see the build TCL for the DAQ2 sets the pcore_tx_lane_sel which is used by the axi_jesd_gt.v to mux the inbound DAC data. Then also the Linux driver is setting the crossbar inside the AD9144 based on the devicetree DTB what appears to be back the other way for DAQ2 but not on DAQ3.
Can you provide some understanding behind the GT lane swapping selections in both the TCL HDL and Linux driver for the AD9144 and other JESD DAC's?
Also in regards to the axi_jesd_gt HDL is there a way to just shut off the receiver section, no GT lane inputs, for a DAC only design?
My main interest is porting the AD9144/AD9136 FMC DAC card over to ZC706/Mini ITX platforms based on the DAQ2 design. The two FMC cards use differing GT lanes out to the AD9144. (I should be able to hack in the AD9517 and SPI differences on AD9144 FMC.)
Note; I currently have the DAQ2 with AD9144 only subsection setup on the Mini ITX platform where I replace the ADI DDS HDL with my own design, which is working well.
The ADI team is doing a outstanding job at supporting the various FMC cards with base HDL, osc app, Linux drivers. Long way in the past few years, setting higher standard for others to follow.