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Some puzzed problem

Question asked by Joshua on Nov 30, 2010
Latest reply on Dec 9, 2010 by CraigG

  Today I do some experiments,and some problem is puzzed me.

 

  Hardware platform:  EZKIT-BF561 & SPI PCB(For SPI Bootting, this is mine.)

  Software  platform:  VDSP 5.0 (Update 8.0)

 

  1) First, I take the example "Power_On_Self_Test", and the ldr is written into the spi flash. then hardware resetting, the flow leds is ok.

      but when i have connected VDSP by ICE-100B, then the hardware reset is done, the flow leds is also running.

 

     In my opinion, The JTAG is the highest priovity, so when connecting with VDSP, the software in spi flash will not run.

     but in this experiment, boot is likely more improtant than jtag.

 

  2) Then i have make a new VDSP project group, that is very easy. it make all leds togglled all the time. when in debugging, it is OK.

    Then following the 1), the ldr is written into flash. but it is in problem.then when i connect VDSP, I run directly(CTRL + F5),donot with building     

    and any other operations, the leds are toggled well.

 

   // CoreA

   main()

   {

          Set_PLL( );

          Init_SDRAM

 

           while(1)

           {

               Toggled_led( );

          }

}

 

// CoreB

     main( )

     {

         Set_PLL( );

         while(1)

          {

               idle( );

          }      

 

     }

 

    How is happened?

    It is likely software is running ok with "glad" JTAG. If there is no jtag, software is in "sad".

 

 

    3) For dubugging boot, "JUMP 0" is added in the start of initial code. then the ldr written into flash. when connecting with VDSP,

       (ONLY HALT.)   there is error"Unable to halt processor,JTAG commnication fail.Possible error at address:0x0002 a000".

      If the bootmode is changed, the connecting is ok.

   

      And someone said in here,"when connecting, make reset active all the time",this is no sense!

 

      So in this case, how can l do it?

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