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ADAU1701 Clocking and PLL

Question asked by rastariot on Nov 30, 2010
Latest reply on Nov 30, 2010 by BrettG

Hi all,


I have a question regarding the clocking and PLL settings. In general I am familiar with MCLK, framesync, Bitclock etc.


I can feed the DSP with various MCLKs starting from 3.072 MHz  and ending up at 24.576 MHz. Fine. And I have an external pin configuration for a PLL which sets a divider. Furthermore in the DSP-Coreregister I can set a samplerate which seems to be more an instruction rate?!


I do not understand what the setting of sample freq in sigmaStudio is used for, because the actual sample freq is determined by the MCLK and the appropriate divider which is the external PLL setting or not? What does this setting in sigmaStudio affect?


Are there any invalid settings? I wrote sigmaDSP support and got a feedback that running the DSP with 24.576 MHz and a PLL setting of 256 is invalid and that the sigmaDSP would not work? Why not, ´cause this would yield to a sample freq of 96kHz which seems to be valid.


Can someone please clarify the things for me?