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AD7760 DVALID Status Bit Problem

Question asked by DST on Apr 7, 2015
Latest reply on May 14, 2015 by jcolao

Hi Analog team,

 

i have a timing problem with the AD7760 dvalid flag:

  • my configuration: ODR = 5MHz, FIR1 = 4x, FIR2 = bypassed, FIR3 = bypassed, ICLK = 20MHz, MCLK = 40MHz
  • init sequence: 1. CntlReg2 = 0x0002, 2. GainReg = 0x8000, 3. OvrReg = 0xFFFF 4. CntlReg2 = 0x0808, 5. readback StatusReg = 0xD008 (readback looks ok)
  • the DRDY pulse period is 200ns -> ok (see attached timing pic: sample clk 120MHz, CursorX - CursorO = 24)
  • after 16 DRDY pulses the DVALID flag is asserted (16 + 0.2ns = 3.2us), but the datasheet tells me that after 1.525us (8 DRDY pulses) the DVALID flag must go high

 

Do you have any idea why the DVALD setup time is two times longer as expected? Is there any misconfiguration?

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