There is a lot of questions related to the sampling rate and data input rate of fmcomms1 (NO OS design).
Still by reading them and reference manuals for AD9122, I did not fully understand how things work. Please
correct me if I am wrong:
Sampling rate that we are setting in main.c is actually DCI rate, not DAC_CLK rate of DAC?
Then that rate is divided by 4 because there is serialization (dac_div_clk = DCI/4)?
I implemented Tx in VHDL, and his output is 32Msps. Now I would like to interface it with fmcomms1, but I am having problems.
When I set sampling rate to 32MHz, I get DAC status not set (probably some PLL did not get locked, that could be reason for that).
I like to hear your opinion what should be easiest way to interface DAC with my Tx.
1. I can do up up sampling for 4 after Tx, and set DCI to 128Msps then I would not get that error (But with this I will consume FPGA logic for up sampling part). Basically with this I would make DUC on FPGA, although AD9122 already has interpolation filters, but it is useless for me to use them, because with them I can increase sampling rate (DAC_CLK) but that would not change DCI rate.
2. Or I can modify axi_ad9122
What you suggest, or you have some smarter option ?
Thank you in advance,