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EVAL ADI-BERT

Question asked by kenton.chu@anstek.com.tw on Apr 7, 2015
Latest reply on May 12, 2015 by Dongfeng

Dear Sir,

 

According to the document UG-551, if it's support the output jitters to 0.4 UI while external clock input (@ 8Gbps,40MHz) in mode 5 ?

 

Thanks in advance.

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