I'm trying to follow the build instructions here : http://wiki.analog.com/resources/fpga/docs/hdl#building_hdl
- Working on a Win 7 64 bit machine
- I downloaded a .zip file (tried with both the master and hdl_2014_r2, same problem)
- after unzipping the file, I launch Vivado 2014.2
- in the tcl console I change to a library component (need to build these before being able to build the project)
- in my case this is : cd i:/hdl-hdl_2014_r2/library/axi_ad9122/
- I source the script : source ./axi_ad9122_ip.tcl
- Vivado starts doing stuff, the Ip package project is setup, filling in vendor name, etc. so that looks good.
The sources from the axi_ad9122 folder are also visible in the sources tab.
- Problem : IP file groups has an exclamation mark, and 30 warning : telling me that the verilog files that are referenced cannot be found, see screenshot - it concerns all files in the 'common' folder. One of the 30 warnings :
[IP_Flow 19-731] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': "i:/hdl-hdl_2014_r2/library/common/ad_mul.v" file path is not relative to the IP root directory.
Looks like there's something wrong with the path and/or environment variable. I can see that the tcl script references 2 other scripts in the ./scripts folder,, looks like something goes wrong. Or does the tcl script only work on linux?