AnsweredAssumed Answered

Clock AD1937

Question asked by Dalle on Apr 2, 2015
Latest reply on Apr 4, 2015 by DaveThib

Hi all


I'm doing a project using that AD 1397 connected to an FPGA. I'm a bit confused about the clock setup of the device. my strategy what's to let the ADC generate clock signals from the ABCLK and ALRCLK pins to the FPGA. I am using an external crystal connected to the MCLKXI and MCLKXO (12.288 MHz) pins and i'm not using standalone mode.


My problem it's that I'm not getting any clock signal out on the ABCLK or ALRCLK pin when measuring with my oscilloscope. In the configuration that I have made via I2C is the ADC and DAC active in PLL and clock control 0 register bit 7 (0x01) and in the ADC control 2 register is the ADC set to be master in bit 3 and 6, and ABCLK it set to be internally generated (0x13) but still no clock signal on the two pins!


Is it even possible to configure the device in this way or have i misunderstood the concept of the device functionality?


I hope you can help me sort out this issue.


Kindly regards

André

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