AnsweredAssumed Answered

Duplicate Test patterns for dual ADC

Question asked by rchan on Mar 30, 2015
Latest reply on Apr 8, 2015 by Anthony.DeSimone

Hi,

I am using a dual ADC ad9652 which comes with a function of setting the LVDS digital output to a number of fixed test patterns. The test patterns include all ones, all zeros, alternating all ones and all zeros and checkerboard. I have used this test mode function for a single ADC without any question. But with a dual ADC, it appears as if each ADC has its own pattern and so the same pattern would appear twice in a row when the output of two ADCs are interleaved on a single 16bit LVDS bus. For example, after setting the register 0x00D in the register map using SPI to the value of 0111binary, the output becomes

0xFFFF,0xFFFF,0x0000,0x0000,0xFFFF,0xFFFF,0x0000,0x0000....

as opposed to an alternating pattern of 0xFFFF and 0x0000.

Is it a correct behaviour?

Cheers,

Raymond

Outcomes