Hi every one.
I´m working with the ad9625 ADC converter in a VC707 development board. Using the reference design with a no-OS configuration.
The FMC board I am testing is not the fmcadc2 but I´ve used that board to check that the HDL code is working, the problem I´ve found is that if I try to work with a different clock speed than 2112MHz I am not able to stablish communication with the ad9625 (Sysref signal always "low level").If I use the 2112MHz clock everything works fine, I can read the JESD lanes and decode the data.
I´ve checked also the register map trying to find some configuration for the clock speed but I´ve found nothing.
The final goal is to make it run with a 1056 MHz clock.
In the datasheet we can found this section:
Any Idea how to change the clock speed? Am I missing something?
Thanks in advance.