We have some questions about SPI timing & design:
1. What is the relationships between CSB & first data for the CSB encompassing all frame mode?
There is some ambiguity (at least from a visual aspect) there s a difference between fig4 & fig6 of AB877 in the place of CSB
falling edge relative to first data.
2. What are the min, max restrictions on stall timing?
3. What drives the data output of the AD9204, rising clock edge or falling clock edge, and to which setup & hold time will it comply?
4. Is there an HDL code of the SPI we can get as reference?