We are working on KC705 + AD9364 to get data loopback from FPGA -> ADI -> FPGA.
We are giving the data to the DAC IP module (util_dac_unpack) from BRAM which we are feeding to the AD9361 IP module. The output from this is given to the ADC IP module (util_adc_pack). Using ILA we are trying to match the output from BRAM and output from ADC.
Before proceeding much with this we wanted to take your inputs whether this is a valid design setup or not?
Also do we need DMA module for giving data to DAC?
Can you also point us to any working details of the AD9361 which tells about the clock and data flow inside the IP? We would like to understand the minimum inputs that should be given to the AD9361 IP module to get the output at the ports: adc_data_i0[15:0] and adc_data_q0[15:0].
All the above mentioned IP modules are taken from the reference design provided by you.
Please provide your inputs so that we can proceed further with our project.