I can not seem to find any documentation on the axi_ad9361 module. There is no documentation on the axi registers locations and what they actually do other than looking at the software code or the hdl code.
There seems to be inconsistencies as well in the RX and TX paths. As far as I can tell for the ad9361 using the DMA input the 16 bit values should be left justified by adding zeros for nibble [3:0] and this will correctly appear on the LVDS outputs. While on the receive side the same is not true. You can not just look at bits 15:4 to get the 12 bit value. Everything seems to be right justified. I have tried playing with the IQ coefficients as well with little luck.
Using the AXI_ad9361 core and the no-os driver , stock out of the box, seems to present the receive data as almost a square wave on the I and Q signals (using chip scope ILA) on the real device. As far as I can tell the same happens in the HDL simulation, but it's hard to tell about what is actually happening on the register reads and writes since the is also no documentation on what the software does either. The software and the hdl both have virtually no comments. I have been able to do produce a call graph using doxygen which helps but it really looks like a lot of spaghetti code. There seems to be no real way of isolating spi read/write code to the part and AXI read write to the hdl CORE which makes any customization very difficult.
I would like to see block diagrams on the HDL core and a register map and a writeup on the software as well. Can anyone point me to where any of this is?