On the ADCLK925, with Vcc = 3.3V and a single-ended clock input, is the worst-case required threshold for a logic high really all the way to the 3.3V rail?
> On the ADCLK925, with Vcc = 3.3V and a single-ended clock input, is the > worst-case required threshold for a logic high really all the way to the 3.3V rail?
No. That is not what this spec is saying. It's saying that VIH can safely up to VCC.
The relevant spec is the "Input Differential Voltage." The spec for VIH single-ended depends on the DC voltage of the complimentary (and assumed unused) input. If you assume that the complimentary input is the customary Vcc-1.3V (which equals 2V in this case), then VIH min is Vcc-1.1V (which is 2.2V in this case). However, VIHmin will track VCC, and if Vcc goes up to 3.4V, then VIHmin increases to 2.3V.
Keep in mind that VILmin is Vcc-1.99V as well.
Basically, everything is Vcc referenced.
Thank you for the answer. One more question:
There still seems to be some overlap between:
V_ILmin = Vee
V_ILmax = Vcc-0.7
(0 to 2.6)
V_IHmin = Vee + 1.6
V_IHmax = Vcc
(1.6 to 3.3)
Is the low threshold overlapping with the high?
I plan to use the circuit shown in Figure 29 of the datasheet, with my ac-coupled single-ended input tied to the ADCLK925's complementary input.
It's entirely possible that there will be overlap between VILmax and VIHmin. In fact, the wider range for common-mode voltage, the more overlap.
None of the ADCLK925 (or any bi-polar LVPECL) receiver specs will make sense if user tries to think of them like CMOS inputs.
CMOS is ground referenced, and usually single-ended. LVPECL is Vcc referenced, and the receiver is fundamentally differential. In this regime, the key specs are common mode voltage and differential voltage swing. As you have discovered, all kinds of inconsistencies result when you try to turn these into ground-referenced single-ended specs.
Thanks again pkern
So we looked at another LVPECL product in the same family, the ADCLK954, and this part has specifications that are easier for us to understand in differential terms because common mode voltage limits are specified directly, see the highlighted text below for “Input common mode voltage”. But when we look at the ADCLK925, it specifies VIH and VIL, which do look like single-ended specifications. If ADI could explain why these two parts are specified in different terms, it would be very helpful to us.
When I posted my last reply it only showed "Thanks pkern" rather than the rest of my followup question. I went back and added the followup question regarding differences in datasheet specifications between similar parts with LVPECL outputs.
It would be clearer if both datasheets were like the ADCLK954. The author of the ADCLK925 datasheet was trying to specify the input voltages in terms of a ground-referenced, single-ended signal. This was done to hopefully make it easier to interface to the part. In the future, I'm going to advocate that we specify the input voltages for bipolar parts like this in the manner of the ADCLK954.
Fortunately, the ADCLK925 datasheet has a spec for the differential input voltage swing, and one can infer the common mode voltage range by looking at Vih/Vil. For instance, it's clear by looking at Vih min on the ACDLK925 that the minimum common mode voltage is 0.8V.
Thanks again pkern! Your explanation really clears things up for me.
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