I am attempting to use the axi_ad9361_dev_if block in my FPGA and I am being asked to implement it without the full digital tuning logic and software that is in the Zed board design HDL ADI provides. In our design, the DATA_CLK/FB_CLK will run at 8 MHz using LVDS mode. The FPGA will be on our own CCA with the trace lengths carefully managed, but then the AD9364 LVDS parallel bus will go to an adapter card(also with careful trace management) and then to a FMCOMMS4 AD9364 evaluation card.
So, the only places the traces and timing are not fully under our control is on the FMCOMMS4 card. Because we are running the DATA_CLK at a reasonable speed, is digital tuning still necessary? This is purely for experimentation purposes in the lab at room temperature. Since this setup is not going into the final product and will only be used at nominal voltage and temperature, I am hoping that gives us some margin as well.
Can you comment?