I am currently trying to set up the AD9361 for using the FIR filter on the RX path.

My clock frequencies are (you can find the Init-struct content below)

BB PLL: 768 MHz

ADC: 96 MHz

HB3 out: 32 MHz

HB2 out: 16 MHz

HB1 out: 8 MHz

FIR out: 8 MHz

I calculated the FIR coefficients using the MATLAB App which led to a filter with 96 taps. This is correct according to UG570 page 34:

"The Rx FIR has two options for its sample clock, either ADC_CLK or ADC_CLK/2. The Rx FIR calculates 16 taps per clock cycle."

--> With FIR being clocked at ADC_CLK/2, I get 96 Taps (ADC_CLK/2/FIR_CLK*16 = 96;Hz/2/8MHz*16=96).

When I apply 96 taps with the no-OS API, I get the following error message:

ad9361_validate_enable_fir: Invalid: ratio ADC/2 / RX_SAMPL * 16 > TAPS (max 64)

Why? Is the documentation wrong or is the API wrong?

One more question: How can I configure the AD9361 to use ADC_CLK as sample clock for the FIR filter? This would allow me using 128 taps which I could use to implement a sharper channel-filter.

Regards,

Oliver

Init struct content to configure the frequencies required:

rx_path_clock_frequencies: | { 768000000, | //OBR: BB PLL 768 MHz | |||||||||||||

192000000/2, | //OBR: Converter 192 MHz | ||||||||||||||

64000000/2, | //OBR: HB3 ratio 3 | ||||||||||||||

32000000/2, | //OBR: HB2 ratio 2 | ||||||||||||||

16000000/2, | //OBR: HB1 ratio 2 | ||||||||||||||

16000000/2}, | //OBR: FIR ratio 1 (can only be set to two after init) | ||||||||||||||

tx_path_clock_frequencies: | { 768000000, | //OBR: BB PLL 768 MHz | |||||||||||||

192000000/2, | //OBR: Converter 192 MHz | ||||||||||||||

64000000/2, | //OBR: HB3 ratio 3 | ||||||||||||||

32000000/2, | //OBR: HB2 ratio 2 | ||||||||||||||

16000000/2, | //OBR: HB1 ratio 2 | ||||||||||||||

16000000/2}, | //OBR: FIR ratio 1 (can only be set to two after init) |

Hi Oliver,

This is strange - the check looks like this:

It should come up with the same max of 96 for your given rates.

We have a look - maybe some rounding issue.

You also see above - where this ADC/2 or not is coming from.

-Michael