One of my customers is making operation test for his prototype unit which utilizes AD9913 DDS on his board.
He has one trouble with AD9913 profile update.
The AD9913 operates in direct switch mode, FSK by profile control pin.
The profile control pin is accessed by FPGA and profile 3(011) and profile 4(100) is utilized for FSK modulation, and other profile is not used.
SYNC_CLK is 200MHz. FPGA doesn’t receive this SYNC_CLK signal. Single clock oscillator drives both DDS and FPGA.
With this configuration, the profile switch action is failed occasionally.
Attached is scope shot for Profile and SYNC_CLK timing, left hand side shows good case and right hand side picture shows failed case.
His current patch is 1) adjustment of Profile signal timing from FPGA (some nsec level) and 2) make I/O Update after 3 SYNC_CLK intervals after switching of the profile.
With these patch, the profile switching action comes good so far.
He would like to confirm with you about these patch is okay or not.
And if you have any other recommendation, please let us know.