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ADV7619 DE and DATA alignment

Question asked by FAE@toronto2 on Mar 25, 2015
Latest reply on Mar 25, 2015 by GuenterL

Hello,

 

We are observing some delays between the DE and DATA signals on the output of the ADV7619. The delay is different and depends on image format (pixel rate) and configuration of the ADV7619 output bus (single or dual pixel per clock, etc). These delays vary from approximately one clock to one clock plus 3ns... 3ns delta seems to be significant for a 6ns clock period?? This is posing some issues for the downstream FPGA...


Does anyone have any comments and/or insight??

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