We are having problems with the AD9548, and would appreciate your help with this matter.

We are working currently in free run mode.

We feed its SYSCLK input with a 10MHz OCXO to get an 1GHz intern frequency,

and set the FTW to obtain 160MHz at the DSS output,

which in turn allows us to generate 10/16/32MHz and 1Hz from its outputs (CMOS mode).

In this case we have a good phase noise on DDS Output (See Figure 1).

If we change FTW a small amount, to obtain (160 MHz - X Hz), the phase noise of the DSS output gets 30 dB worst around X Hz. (See Figure 2, where X=104Hz).

Much of this seems to be noise from the outputs (CMOS), and it just disappears if we power down the outputs, but there is still some spurious phase noise at frequency X Hz (See Figure 3, where X=104Hz).

Note also that for different values of X, from 50 Hz to 2kHz, we get similar phase noise deterioration around frequency X Hz.

What we would like to know is:

1) What can we do to eliminate the spurious in Figure 3?

We think the output stage could be just multiplying it, and solving this problem the phase noise would be normal.

2) Are phase noise graphs in AD9548’s datasheet valid for CMOS outputs?

We see in the datasheet that jitter specs are valid for all output modes, but phase noise graphs are only given for LVPECL.

Also, we tied all AVDD3 pins together as suggested in the DS when using 3.3V, but maybe for CMOS outputs we should have made otherwise.

Thanks for your assistance,

Hello Hank,

> 1) What can we do to eliminate the spurious in Figure 3? We think the output

> stage could be just multiplying it, and solving this problem the phase noise would be normal.

I'm not sure you can fully eliminate them, but you can sure surely limit them. You can change the reconstruction filter to permit a DDS frequency of 320 MHz, or design the reconstruction filter for 160 MHz, which should allow the reconstruction filter to filter unwanted spurs more effectively. The other trick is choosing a system clock frequency that's a little bit off of 1 GHz. We normally try to not have the system clock clock be integer related to the output frequency so that close-in spurs are better. Therefore, you may get better results with a 19.2 MHz OCXO.

2) Are phase noise graphs in AD9548’s datasheet valid for CMOS outputs?

We see in the datasheet that jitter specs are valid for all output modes, but phase noise graphs are only given for LVPECL.

> Also, we tied all AVDD3 pins together as suggested in the DS when using 3.3V,

> but maybe for CMOS outputs we should have made otherwise.

Yes. CMOS tends the make life difficult for power supplies and noise in general. Isolating the 3.3V output driver power supply will help.

-Paul