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Interfacing Vivado FIR Compiler 7.1

Question asked by jeffkt2 on Mar 23, 2015
Latest reply on Mar 27, 2015 by CsomI

Hi,

 

Not sure if this is an appropriate place to post this, but maybe someone could help. I'm working with a ZED board and FMCOMMS1, and I'm trying to customize the hardware based off the no-os reference design. I'm having some issues using the FIR Compiler IP block in Vivado.

 

My basic test is to apply an impulse to the FIR IP block with an AXI-Stream interface and observe the output. I'm not quite getting any output, and I was wondering if someone could take a look and let me know if I'm doing anything obviously wrong.

 

I have created a custom impulse generator block that simply produces impulses on an AXIS interface to feed the FIR block.

 

fir_test_block.png

 

The AXIS interface have been broken out for observation. The resulting simulation gives me the following:

 

fir_test_sim.png

 

After reset, the FIR AXIS slave asserts TREADY and the impulse generator starts to generate pulses. However after a few clock cycles, TREADY goes down, so the impulse generator stops. The FIR output never produces anything. Am I missing any settings or driving the interface improperly? The FIR Compiler Interface tab has the option for Output TREADY. I've tried to check that box to and force TREADY always high, and the results look the same.

 

Thanks for any help!

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