I need help to utilize the AD9959 DDS chip to work in Quad SPI mode. My current design (not a reference board) works in single SPI mode, but I have not yet been able to make it work in Quad SPI mode. I have verified with a logic analyzer that the quad data I am sending on SDIO_0 – SDIO_3 looks exactly like figure 45 of the 44 page AD9959 data sheet. The logic analyzer reads the same data I am attempting to write to the AD9959, so I don’t believe this is a hardware issue. I suspect that I am not configuring the registers correctly.
The approach I am taking to test the Quad SPI functionality is as follows. Steps 2-11 are run on an NXP processor within a test function.
- Bring up the AD9959 in single SPI mode, and verify that I can write a frequency to one of the channels. Then write test data into registers CW4, CW10 & CW12, read it back and verify that the rad-back data is correct.
- Still in single SPI mode, write to the CSR register at 0x0 the value 0xF6. This should enable all four channels and set CSR[2:1] bits both high which is required for quad SPI mode.
- Write logic zero to clear the SDIO_0 – SDIO_3 and IOUpdate control signals.
- Toggle the IOUpdate signal high and back low again for several sync clock periods
- Send a command to re-route an FPGA mux from single SPI to quad SPI. From here on the four SDIO signals are bit-banged by an NXP arm processor through the FPGA to the DDS SDIO pins.
- Write the same data to registers CW4, CW10 & CW12 that successfully programmed these registers while in single SPI mode, but this time use a Quad-SPI bit-bang function. Use a logic analyzer to verify data looks like figure 45 of AD9959 data sheet.
- Just in case, reset IOUpdate signals to be sure they are still low.
- Toggle the master reset of the DDS (pin 3) to force the internal registers to their default state.
- Configure the ADD9959 as follows in preparation to be read in single bit mode as before: To register FR1 write configuration data 0x94, 0x00, 0x00. To register CSR write the configuration data 0xF2 to enable all channels and set CSR[2:1] = 01 for single bit mode.
- Toggle the IOUpdate signal high and back low again for several sync clock periods.
- Switch the FPGA mux back to single SPI mode in order to read back the data that was programmed into the DDS registers in quad SPI mode. This is tested code.
- The data being read back in single bit mode reads all FFs
Note: If the AD9959 is not reset in step 8, the data read back in single bit mode is all FFs.
I would appreciate any help I can get.