The 9361 and 9364 Reference Manuals only show the timing waveforms for single SPI write and read. Can ADI provide the timing diagrams for multi-byte writes and reads? Or, point me to an equivalent specification on-line?
On page 105 of the 9364 Reference Manual, in the paragraph titled "Example: MSB-First Multibyte Transfer", it says that 16 extra clocks must be provided after the fourth byte and can be used to clock in the next instruction. If I don't want to clock in the next instruction, do I drive zeros on the SPI_DI for those sixteen clocks? Or, will bringing SPI_ENB high at the end of those 16 clocks cancel the instruction? Or, do I just bring SPI_ENB high after the end of the fourth byte.