First I open from directory cf_ad9361_zed HDL reference code using "Xilinx Platform Studio Project" program. After that I try to Complile HDL reference code using "Generate BitStream" button, but I get few errors. Listed below:
Unknown Tcl procedure ::hw_axi_ad9361_v1_00_a::run_coregen called
ERROR:EDK - axi_ad9361_0 (axi_ad9361) -
INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_2.
INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_3.
ERROR:EDK:440 - platgen failed with errors!
Could somebody tell me what causes these errors and how I can fix them ?. I would like to drive "Generate Bitstream" trought without any errors.