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How to best select the phase noise integration limits for jitter calculation?

Question asked by languer on Nov 24, 2010
Latest reply on Nov 24, 2010 by languer

We have an application where we are looking at utilizing IF sampling on an ADC. We've read that for IF sampling applications jitter on the reference/samlping clock is more limiting than in regular ADC sampling applications due to the higher frequency content. Looking at the literature available on the subject we understand this; even the best TCXOs can have poor jitter performance, mainly if a lower integration limit of the phase noise mask is used. So far we have been integrating down to 10Hz (which is the manufacturer's lowere published limit).


Recently I read an article that mentioned to place the upper limit at double the encode clock frequency, and the lower limit at the specified minimum frequency resolution of the system. I noticed that in most examples, the lower limit never goes below 100Hz (most cases is 1kHz or 10kHz). Does anybody have more information on this subject? How to properly select the integration limits, and what is the driver behind the selection?