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ad6676 reference design

Question asked by nemo45 on Mar 21, 2015
Latest reply on Mar 27, 2015 by rejeesh

Hi,

 

In AD6676 refence design the ADC data comes out of the "axi_ad6676_gt" block from rx_data[63:0] and rx_clk_g outputs. I have sampling rate set as 200MHz and expecting to receive 16bit I and Q samples at 200MHz rate. How should I interpret these 64bit data output to get the I,Q samples?

 

Regards

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