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AD9364 calibrates and BIST works, but not output from P1

Question asked by arvabj on Mar 20, 2015
Latest reply on Mar 24, 2015 by tlili

I am bringing up a full-custom FPGA + FMCOMMS4-EBZ board with custom HDL based SPI drivers. I have been successful in calibrating the AD9364 as it is performed in the ADI Non-OS drivers (as per the ad9361_init() function). But i use my own SPI writes and read routines in HDL. The AD9364 calibrates all the way through, the PLLs lock and the device is put in FDD with all calibrations done (Register 0x017 = 0x1A after all calibration steps)

 

I can enable BIST tones and see the RF output at the programmed frequency, LO, SSB component etc. But when i try to send out data patterns from the P1 port, i do not see any RF output. I can just see the LO leakage out. I have configured the device for Dual Port, Full Duplex, CMOS mode (Registers 0x010 = 0xC8, 0x011 = 0x00, 0x012 = 0x02) and i am following the timing diagram as shown in figure-71 of UG-673 for AD9364.

 

Seems like the P1 port buffers are disabled to me. I can even probe the test-points for FB_CLK_P, Tx_Frame_P and Rx_D0/5_P on the FMCOMMS4-EBZ and see that all the signals are reaching the board. I do not see any reason why i should not see an output with my test patterns on P1 port. I do not see any registers other than x010, x011, x012 for port configurations.

 

I understand ADI does not support individual SPI drivers. But any pointers on where to look for potential problems with the P1 port enable or any particular initialization function in the Non-OS driver to look at closely will be very helpful.

 

thanks in advance.

AB

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