Dear support team,
I have a question about hibernate bit(0xF400 0bit) in initialization sequence.
In Datasheet P.26, "Recommended Program/Parameter loading Procedure" said that
"When writing large amounts of data to the program or parameter RAM in direct write mode,
use the hibernate register(Address 0xF400) to disable the processor."
In capture window, I think the sequence of disable the processor are below red line block :
And I think the sequence of enable the processor are below red line block:
At this enable sequence , I think that Hibernate bit should be clear before rising edge of START_CORE bit.
And current sequence of SigmaStudio is invalid , I think.
Because Hibernate bit enabling and CORE_START bit enabling are conflictive.
Could you tell me your opinion about it,please?
If sigmastudio's sequence is correct,
could you tell me delay time of "start delay" before clearing hibernate bit,please?