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About AD9548 DPLL register setting

Question asked by kenton.chu@anstek.com.tw on Mar 20, 2015
Latest reply on Mar 27, 2015 by pkern

Dear Sir,

 

I have a little confused about the DPLL setting. If someone kind to guide how to set the related registers ? How is the value of external loop filter ? Pls give some recommend to attached which the related value calculated by excel. Thanks.

 

For application is as below,

 

1. SYSCLKP by crystal 19.44 MHz

2. Refence A is 1Hz (LVDS 0~3.3V)

3. OUT0 is 14.11 MHz

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