AnsweredAssumed Answered

AD1974 sample rate setting.

Question asked by sss on Mar 20, 2015
Latest reply on Mar 24, 2015 by sss

Hi,all.

 

I'm confused the clock signal relation & register setting,

MCLK,sample rate,ALRCLK,ABCLK @AD1974.

 

In the datasheet 11page "CLOCK SIGNALS",  I found the following description.

"In 96 kHz mode, the master clock frequency stays at the same absolute frequency;

therefore, the actual multiplication rate is divided by 2.

If the AD1974 is then switched to 96 kHz operation (by writing to the SPI port),

the frequency of the master clock should remain at 12.288 MHz (128 × fS)."

 

I will evaluate the 96 kHz stereo mode,

MCLK:12.288 MHz(128 × fS >>> 256 × fS × 1/2 ?)

Sample Rate:96KHz

 

Q1.

Following value is correct?

ALRCLK:fs = 96KHz

ABCLK:64 × fS = 64 × 96KHz = 6.144MHz

 

Q2.

In the PLL and Clock Control 0 and others, I cannot find register for changing to "128 × fS" mode .

How to configure the 96KHz mode, "256 × fS × 1/2" ?

ADC Control 0[7:6] 01, and other register ?

 

Best Regards,

sss

Outcomes