AnsweredAssumed Answered

AD9361 for maximum bandwidth

Question asked by arvabj on Mar 19, 2015
Latest reply on Mar 25, 2015 by rgetz

There was no response to my question earlier. so i am re-posting my questions regarding AD9361 setup


1. Is it necessary to use the internal interpolation/ decimation filters ? For power savings, can i keep the sampling rate up to the ADC and DAC as 61.44MHz (bypass or interp/decim by 1 throughout) using a 983.04MHz BBPLL clock ?



2. Can the ADC be clocked at 491.52 MHz ? From the datasheet, in LVDS mode the DATA_CLK can be as high as 245.76MHz. I thought that also applies to the ADC/ DAC maximum rates. Can you please verify ?



3. What is the overall constraint on maximum clock rates for the interp/decim/FIR filters and the ADC/DAC ? My understanding was 61.44MHz for filters,ADC,DAC in CMOS mode and 245.76MHz for filters,ADC/DAC in LVDS mode. Please clarify.



Thanks again,