We have designed a PCB to give PAL output. The board is connected to a FPGA module so I can modify the necessary inputs to ADV7393.
However, we have a problem. We have two televisions with the same brand but different model. One of the TVs gives very good output. However, the other TV rarely gives the true output. When I give internally generated test pattern to the TV, it shows perfectly the vertical colored frame. Probably, the input (digital waveform) which I provide is not perfectly suitable for ADV7393.
I provide 27 MHz clock to the ADV7393. The frame is composed of 625 lines as in Figure 112. (SD Timing Mode 2, Slave Option, PAL) (in the datasheet). The line is composed of 1536 cycles ((Y and CrCb) x 768). HSYNC and VSYNC pulse width is one clock cycle (I also increased the pulse width but it did not work).
I tried to explain as detailed as possible. What could be the problem?
Thank you for your time.
Configuration for the internally generated test pattern:
Configuration for the designed system: