Hi All,

Maybe this is more question for Xilinx forum, but let me try. I incorporate my TxRx design into

reference design (I made some modifications of Reference Design), but utilization of LUT is pretty high (73%), and

it should not be like that (especially for Rx side). In same time utilization of DSP slices is really

low (39%), just axi_ad9122 and axi_ad9643 are making utilization of DSP slices. What I would

like to do is to make optimization of design (to change my Verilog code). I would like to use DSP

slices on FPGA for multiplication rather then using logic slices for that. Is there some guidline how

to target DSP slices on Zynq from HDL, or generally how I can do it.

Again sorry if question is not directly related to Analog devices product, but I see that you already

did that with axi_adxxx (they are utilizing DSP slices).

Kind Regards,

Definitely Xilinx has the official word.

If you do not want to directly instantiate them- the following are alternatives - remember these are just hints-- you might have to rewrite the equations so that the tool will catch up.

always @(clock'edge)

product = a*b-c; // or any of the valid equations it supports

product_d1 <= product;

product_d2 <= product_d1;

end

Make sure you get the bus-widths correct.

This is the simple approach if you do not want to caught up in the details.