Hi Dragos and everyone,
I recently made a few post about the problem of the adc_capture function when running with ad9364 on a zynq board. See https://ez.analog.com/message/179065#179065.
When I traced the problem, I found the error origins from the FPGA. I am using vivado 14.4 using the hdl-hdl_2014_r2 libraries, when I opened synthesised design, I found that the dest_response_eot (line 376 in request_arb.v) is optimized away by the tool. This ends up with not EOT signal generated and hence return non-end signals when we pull the IRQ_PENDING register in the software. However, I had no problem when I am doing the same thing in vivado 14.2. Is there a quick fix (I've tried the synthesis attribute 'KEEP' but didn't work) that I can get around with it.