I designed a PCB that includes an AD9522-1 that I intend to use for clock distribution. The supporting circuitry for the AD9522-1 is basically a copy of the AD9522/PCBZ Evaluation Board (which I also use to program the AD9522-1 in my design by means of the AD9522 Evaluation Software).
I program the AD9522-1 in order to output several clks of 200 MHz locked to a 10 MHz input signal. I use the following configuration:
- Operational Mode: Internal VCO and CLK Distribution
- PLL Mode: Norm Op
- REF1: 10 MHz input
- R Divider =1
- N Divider=240
- VCO Divider=2
- Channel Divider=6
This configuration works fine when using the Eval Board. However, I am unable to get an clk output when using my design. At the most, I get a high level signal when I program an output channel in CMOS format. Using the STATUS pin, I have verified the following:
- The R Divider Output is correct.
- The N Divider Output is always low.
Even though the absolute absence of an output signal suggests me that it is not a problem of the external loop nor the charge pump current, I have tried changing these parameters with no success. As for a chip or soldering failure, I get the same results in three different PCBs.
My feeling is that I am missing something quite basic, any suggestions?
Thank you very much.