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ADSP-21489

Question asked by nitin@anglia on Mar 16, 2015
Latest reply on Mar 27, 2015 by Harshit.Gaharwar

I have a system where ADSP-21489 is dealing with 3 clock domains, Input Clock, Local Clock and Output clock. Data Rate match them through using internal Block RAM/ROM to overcome clock differences because of ppm. So SPDIF Input @ CLK1 is first stored in Block0&1 and then RAM is read from Local Clock or DSP core clock, data is processed and written to Block3&4 and then it read out @ CLK3 using DIP Peripheral.

Could the system handle multiple clocks and Rate matching is possible through Block RAMs. Are these Block RAM bounded together or they can be used independently?

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