I am trying to generate LO using ADF4106 and V950ME08-LF.
I am using development board of ADF4106 and SDP.
When i am configuring the part for 4450MHz it is fine but when i am try to generate 5089MHz it is not going more than 4489MHz.
tuning voltege of VCO is 0 to 9.5V and ADF4106 supports up to 5.5V. How can generate the my required LO.
I have installed the loop filter as given in ref design in PLL sim software.
J S Hyanki