I was trying to look into the example codes of SPI core driven there i could find transmission done in a for loop,now i want this to be done interrupt based.
1)As there are 2 SPI port cant i use the same port for transmit & receieve with interrupt.
2)In core driven method how do i check the status of buffer ,as in the manual it is given that check the buffer status before reading from or writing to these registers because the core does not hang when it attempts to read from an empty buffer or write to a full buffer.
3)I am not able to get the whole concept of CLKPL & CPHASE.
4)Why is MISO diabled in the examole code.
5)What is the condition for interrupt generation in core driven method is it the like when transmit buffer is not full or receieve buffer is not empty.