I am using the axi_ad9122 in fmcomms1 hdl design with parameters SERDES 0 and MMCM 0. In the software side when it gives the dac setup it is showing DAC setup: dac_clock <64MHz> while I am setting the sampling rate at 16 MHz. So the clock ratio is 4 from the register 0x4058 of axi_ad9122. I was wondering where this register is written. From which parameter inside the hdl code?